Non-volatile memory devices, such as EPROM, EEPROM, and Flash EEPROM, store data even after power is turned off. One common application of EEPROMs is in programmable logic devices (PLDs). PLDs are standard semiconductor components purchased by systems manufacturers in a “blank” state that can be custom configured into a virtually unlimited number of specific logic functions. PLDs provide system designers with the ability to quickly create custom logic functions to provide product differentiation without sacrificing rapid time to market. PLDs may be reprogrammable, meaning that the logic configuration can be modified after the initial programming.
The manufacturing of PLDs has moved progressively toward defining smaller device features, characterized by the channel length of transistors. As feature sizes shrink, the conventional EEPROM structure has given way to different cell designs and array architectures, all intended to increase density and reliability in the resulting circuit. In most cases, cell designers strive for designs which are reliable, scalable, cost effective to manufacture and able to operate at lower power, in order for manufacturers to compete in the semiconductor industry.
Typically, in programmable logic EEPROM devices, in order to store a logical zero, electrons are injected onto a floating gate of a transistor to provide a negative voltage on the floating gate, thus increasing the control gate threshold voltage needed to turn on the transistor. This is done by causing electrons to tunnel through a tunnel oxide layer, or “tunnel opening,” to the floating gate. Conversely, to store a logical one, the floating gate is discharged and the threshold voltage is decreased by causing electrons on the floating gate to tunnel through the tunnel opening in the opposite direction.
One example of a commercially successful EEPROM structure for programmable logic applications is shown in U.S. Pat. No. 4,924,278 (hereinafter “the '278 patent”), issued to Stewart Logie on May 8, 1990 and assigned to Advanced Micro Devices, Inc., Sunnyvale, Calif.
FIGS. 1 and 2 show a schematic diagram and a cross-section, respectively, of one embodiment of the EEPROM structure shown in the '278 patent. The EEPROM structure uses a single layer of polycrystalline silicon and a control gate formed in the silicon substrate to eliminate the need to form a separate control gate and floating gate in layers of poly silicon. The EEPROM structure is made up of three separate NMOS transistors: a write transistor, a read transistor, and a sense transistor. In order to “program” the floating gate of the sense transistor, a net positive charge is placed on the gate by causing free electrons from the floating gate to tunnel into the source region of the write transistor through the tunnel opening. Likewise, to erase the floating gate, the floating gate is given a net negative charge by causing electrons to tunnel from the source region onto the floating gate through the tunnel opening.
FIG. 2 shows a standard EEPROM memory cell 10. A P-type substrate 5 has N+ type regions formed on and below its surface by standard diffusion techniques. These N+ type regions correspond to the source and drain regions of the three transistors that make up the EEPROM memory circuit. Write transistor 20 comprises drain 22, source 24, channel region 25, gate oxide layer 27 and control gate 28. Sense transistor 30 comprises drain 32, source 34, channel region 35, gate oxide layer 37, and N-type polycrystalline silicon (poly-Si) floating gate 38. Read transistor 40 comprises drain 41, source 32, which is also the drain of sense transistor 30, channel region 45, gate oxide layer 47, and control gate 48. Poly-Si floating gate 38 is capacitively coupled to source 34 of sense transistor 30, via gate oxide layer 37 (approximately 300 .ANG. in thickness), and capacitively coupled to source 24 of write transistor 20 via tunnel oxide layer 55 (approximately 90 .ANG. in thickness). Poly-Si floating gate 38 also extends over channel region 35 of sense transistor 30 so that when a sufficient positive charge is on poly-Si floating gate 38, channel 35 will invert and conduct current between source 34 and drain 32 of sense transistor 30. Field oxide layer 57 insulates floating gate 38 from the underlying substrate 5 separating sense transistor 30 and write transistor 20.
Operation of the memory cell 10 will be described with reference to FIGS. 1 and 2. In FIG. 1 word line WL is connected to control gates 28 and 48 of write transistor 20 and read transistor 40, respectively. Tunnel oxide layer 55 (the tunnel opening) is represented by capacitor Ct while gate oxide layer 37 between source 34 of sense transistor 30 and poly-Si floating gate 38 is represented by capacitor Cg. Drain and source contacts are represented by D and S, respectively.
The three operations of the memory circuit are write, erase, and read. The various voltages applied to the circuit of FIG. 3 are shown in Table 1.
TABLE 1Sub-WLWriteReadSourcestrateControlWLRReadVccgroundVsensegroundgroundgroundVccProgramVppVppHiZgroundgroundgroundgroundEraseVppgroundHiZVppgroundVppVcc
When N type poly-Si floating gate 38 is written upon, or programmed, floating gate 38 is given a positive charge by removing free electrons from floating gate 38. To accomplish this, first, a high programming voltage Vpp is applied to word line WL, which turns on write and read transistors 20 and 40. By turning on transistor 20, a write signal applied to drain 22 of write transistor 20 is coupled to source 24. Similarly, when transistor 40 is on, a read signal applied to drain 41 of read transistor 40 is coupled to source 32 of read transistor 40. Next, in order to program sense transistor 30, high programming voltage Vpp is applied to drain 22 of write transistor 20, while source 34 of sense transistor 30, as well as drain 41 of read transistor 40 and substrate 5, are grounded. Because source 24 of write transistor 20 is at a high voltage and source 34 of sense transistor 30 is grounded, voltage is capacitively coupled to poly-Si floating gate 38 due to the electric field created between source 24 and source 34 through gate oxide layer 37 and tunnel oxide layer 55.
Because the capacitance between source 24 and floating gate 38 across tunnel oxide layer 55 is very small (on the order of 0.004 pF), and the capacitance between source 34 and floating gate 38 across gate oxide layer 37 is about ten times greater, a large percentage (on the order of 90%) of the voltage difference between source 24 and source 34 (i.e., Vpp) appears between source 24 and floating gate 38 across tunnel oxide layer 55. This voltage is sufficient to cause electron tunneling from floating gate 38 to source 24 of write transistor 20 through tunnel oxide layer 55, resulting in a net positive charge on floating gate 38. The positive charge is sufficient to turn on sense transistor 30 because floating gate 38 extends over channel region 35 of sense transistor 30. This indicates a logical 1 since current can flow through sense transistor 30 during a read operation.
To erase floating gate 38, high programming voltage Vpp is applied to word line WL as well as source 34 of sense transistor 30 and drain 41 of read transistor 40, while drain 22 of write transistor 20 and substrate 5 are grounded. In this biasing arrangement, the high voltage at source 34 of sense transistor 30 is capacitively coupled to floating gate 38 and almost all of high programming voltage Vpp appears across tunnel oxide layer 55 between floating gate 38 and grounded source 24. This causes electrons from source 24 to tunnel through tunnel oxide layer 55, resulting in a net negative charge on floating gate 38. Thus, channel 35 of sense transistor 30 is not inverted and sense transistor 30 is shut off.
The size (i.e., area) of the tunnel opening is obviously important to ensure proper operation of the memory cell 10. However, the size of the tunnel opening is also an important factor in the determining the overall size of the memory cell. If the tunnel opening size can be reduced while maintaining low defects and proper operation, then the overall memory cell can also be reduced. Reducing the size of a memory cell adds up to significant savings in chip real estate when multiplied by the millions of memory cells in a PLD.
FIG. 3 shows a graph of a curve representing yield versus tunnel opening size. A target point (shown at 60) is considered an ideal yield-versus-size tradeoff. As can be seen, the yield drops off significantly below the target point 60 as the tunnel opening size is further reduced. This drop off in yield is caused by limitations in non-linear optical systems used during fabrication. Conversely, tunnel opening sizes larger than the target point unnecessarily increase memory cell size without a corresponding increase in yield.
Unfortunately, there is no simple technique for determining the target point 60 of FIG. 3. For example, there is no standardized techniques for determining the smallest tunnel opening size in a memory cell for a given technology and no standardized techniques for determining the defect density for a given tunnel opening size.